1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit having a comparator and a sampling circuit.
2. Description of Related Art
In recent years, as the speed of electric signals increases and circuit size of an entire semiconductor device used in electric equipments becomes larger, it is desired to miniaturize and reduce power consumption of semiconductor devices. In connection with this, it is becoming important to miniaturize and reduce power consumption of a comparator, which is one of basic circuit configuration of a semiconductor device. The comparator here is a device for an Analog-to-Digital (A/D) conversion which compares two input voltages and outputs the size relation thereof as a digital value.
Although the dynamic comparator circuit disclosed in Japanese Patent Publication No. 02-34490 has an advantage as compared to a comparator circuit of a related art that it is highly sensitive to an input voltage difference with its comparatively small circuit size and the power consumption in the standby and operating time is low. Therefore, dynamic comparators are becoming to be widely used in recent years.
FIG. 1 is a circuit diagram of a dynamic comparator 70 disclosed in Japanese Patent Publication No. 02-34490. The configuration and the operation of the dynamic comparator 70 are explained with reference to FIG. 1.
In FIG. 1, the dynamic comparator 70 includes a first flip-flop which is composed of a pair of cross-coupled N type transistors MN2 and MN3 and initial stage input signal transistors 71 and 72 which have common sources and drains with the N type transistors MN2 and MN3 that make up the first flip-flop.
The dynamic comparator further includes a second flip-flop which is of opposite polarity to the first flip-flop and is composed of a pair of cross-coupled P type transistors MP1 and MP2. Further, the dynamic comparator includes P type transistors MP0 and MP3 which have common sources and drains with the P type transistors MP1 and MP2 that make up the second flip-flop.
Furthermore, drains and sources of N type transistors MN6 and MN7 are respectively connected between the drains of the P type transistors MP1 and MP2 and drains of the N type transistors MN2 and MN3. Gates of the P type transistors MP0 and MP3, and N type transistors MN6 and MN7 are connected to a mode switching terminal 4. A pulse signal is input to the mode switching terminal. Gates of the initial stage input signal transistors 71 and 72 are respectively connected to an input signal input terminal 8 and a reference potential input terminal 9. Voltages to be compared are externally input to the input terminals.
Moreover, the drains of the N type transistors MN6 and MN7 are respectively connected to output nodes CMPB and CMP. Furthermore, sources of the N type transistors MN2 and MN3, the initial stage input signal transistors 71 and 72, and N type transistors MN8 and MN9 are connected to a low potential power supply Vss. On the other hand, the P type transistors MP0, MP1, MP2, MP3, MP4 and MP5 are connected to a high potential power supply Vdd.
Next, the operation of the dynamic comparator 70 is explained with reference to FIG. 1. There are two operation modes for the dynamic comparator 70, which are a standby mode and a comparison mode.
When the mode switching terminal 4 is at Low level, the dynamic comparator 70 goes into the standby mode. In the standby mode, the output nodes CMPB and CMP are reset to High level. When the dynamic comparator 70 goes into the comparison mode, preparations for injecting a current into the first flip-flop, which is composed of the N type transistors MN2 and MN3, is performed.
When the mode switching terminal 4 is changed to High level, the dynamic comparator 70 goes into the comparison mode. In the comparison mode, the dynamic comparator 70 compares a potential difference of the input signal input terminal 8 and the reference potential input terminal 9. Then the dynamic comparator 70 outputs the result to the output node CMP by logic signal voltage. Detailed operation is explained with reference to FIG. 1.
A transition of the mode switching terminal 4 from Low level to High level causes the P type transistors MP0 and MP3 to be non-conducting state, and the N type transistors MN6 and MN7 to be conducting state. A current flows into input nodes CN1 and CN2 via the N type transistors MN6 and MN7, and the potentials of the input nodes CN1 and CN2 begin to increase. If the potential of the input signal input terminal 8 is higher than that of the reference potential input terminal 9, the potential of the input node CN2 exceeds a threshold voltage of the N type transistor MN2 before the potential of the input node CN1. This is because that the current flowing into the initial step input signal transistor 72 is smaller than the current flowing into the initial stage input signal transistor 71. As a result, a current begins to flow also into the N type transistor MN2, and the potential of the input node CN1 will not increase. On the other hand, the potential of the input node CN2 continues to increase, and the potential difference of the input nodes CN1 and CN2 increases rapidly.
This potential difference is transmitted to the second flip-flop, which is composed of the P type transistors MP1 and MP2. Then, similarly, the potential difference of the output nodes CMPB and CMP increases rapidly.
That is, the dynamic comparator 70 realizes functionalities which are highly sensitive to an input potential difference and is capable of high-speed output response to an input signal by the increased potential difference between the input nodes CN1 and CN2 using the double flip-flops.
It is noted that the comparator disclosed by Japanese Unexamined Patent Application Publication No. 2002-237743 is one of application circuits using this kind of comparator.